The CDB/HCDB semiconductor wafer representation serverWALKER, D. M. H; KELLEN, C. S; SVOBODA, D. M et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1993, Vol 12, Num 2, pp 283-295, issn 0278-0070Article

DVLASIC : catastrophic fault yield simulation in a distributed processing environmentWALKER, D. M. H; NYDICK, D. S.IEEE transactions on computer-aided design of integrated circuits and systems. 1990, Vol 9, Num 6, pp 655-664, issn 0278-0070, 10 p.Article

On comparison of NCR effectiveness with a reduced I_DDQ vector setSABADE, Sagar; WALKER, D. M. H.IEEE VLSI test symposium. 2004, pp 65-70, isbn 0-7695-2134-7, 1Vol, 6 p.Conference Paper

Comparison of effectiveness of current ratio and delta-I_DDQtestsSABADE, Sagar S; WALKER, D. M. H.International Conference on Embedded Systems DesignInternational Conference on VLSI Design. 2004, pp 889-894, isbn 0-7695-2072-3, 1Vol, 6 p.Conference Paper

K longest paths per gate (KLPG) test generation for scan-based sequential circuitsWANGQI QIU; JING WANG; WALKER, D. M. H et al.International Test Conference. 2004, pp 223-231, isbn 0-7803-8580-2, 1Vol, 9 p.Conference Paper

IC performance prediction for test cost reductionJUNGRAN LEE; WALKER, D. M. H; MILOR, L et al.IEEE international symposium on semiconductor manufacturing conference. 1999, pp 111-114, isbn 0-7803-5403-6Conference Paper

Application of defect simulation as a tool for more efficient failure analysisGRIEP, S; KHARE, J; LEMME, R et al.Quality and reliability engineering international. 1994, Vol 10, Num 4, pp 297-302, issn 0748-8017Conference Paper

A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variationsGULATI, Kanupriya; JAYAKUMAR, Nikhil; KHATRI, Sunil P et al.Integration (Amsterdam). 2008, Vol 41, Num 3, pp 399-412, issn 0167-9260, 14 p.Article

Estimation of fault-free leakage current using wafer-level spatial informationSABADE, Sagar S; WALKER, D. M. H.IEEE transactions on very large scale integration (VLSI) systems. 2006, Vol 14, Num 1, pp 91-94, issn 1063-8210, 4 p.Article

Hierarchical mapping of spot defects to catastrophic faults : design and applicationsGAITONDE, D. D; WALKER, D. M. H.IEEE transactions on semiconductor manufacturing. 1995, Vol 8, Num 2, pp 167-177, issn 0894-6507Article